Volt-second unbalanced compensated two core power transformer

ABSTRACT

A two-core dc to dc converter power transformer having duo reset coils circuit interconnected for compensating volt-second unbalance. The circuit interconnect between the reset coils on both cores includes current limiting means limiting current flow after core reset to saturation and diode signal rectifying means.

United States Patent Gregorich [54] VOLT-SECOND UNBALANCED COMPENSATEDTWO CORE POWER TRANSFORMER [72] Inventor: James M. Gregorich, Marlboro,Mass.

[73] Assignee: Collins Radio Company, Cedar Rapids,

Iowa

[22] Filed: June 10, 1971 [21] App1.No.: 151,666

[52] U.S.Cl ..321/2,321/l1,321/25, l 321/45 R, 331/113 A [51] Int. Cl...I-I02m 3/14 [58] FieldofSearch ..321/2, 11,25,45 R;

CORE #2 in UNIT-{I UNBALANCE CORE 1 51 Apr. 25, 1972 [56] ReferencesCited UNITED STATES PATENTS 3,223,945 12/1965 Damon ..331/113 A3,275,948 9/1966 Rosenbusch.. ....33l/113 A 3,473,104 10/1969 Tate..321/45 R 3,492,562 1/1970 Genuit... ....321/2 X 3,526,823 9/1970Genuit ....321/2 3,541,428 11/1970 Schwarz ..321/2 PrimaryExaminer-William I-I. Beha, Jr. Attorney-Warren I-I. Kintzinger and R.J. Crawford [57] ABSTRACT A two-core dc to dc converter powertransformer having duo reset coils circuit interconnected forcompensating voltsecond unbalance. The circuit interconnect between thereset coils on both cores includes current limiting means limitingcurrent flow after core reset to saturation and diode signal rectifyingmeans.

8 Claims, 4 Drawing Figures LOAD Patented April 25, 1972 3 Sheets-Sheetl NPN 12 95 UNBALANCE f SIGNAL SOURCE NPN SUPPLY MAX CORE #2 1 Q1 UN|T-INPN l2 UNBALANCE SIGNAL SOURCE DC SUPPLY U IO /8 2 p 22 N2 f Q5 20 LOADQ5 UNBALANCE J F|G 2 CORE#| INVENTOR JAMES M. GREGOR/CH IJented April25, 1972 I 3 Sheets-Sheet 2 25' TI F NPN Li LOAD SIGNAL SOURCE NPN 0c /6SUPPLY INVENTOR JAMES M. GREGORICH Patented April 25,

Ql BASE DRIVE 0 Q2 BASE DRIVE 0 I I 20v 0| v COLLECTOR o Q2 COLLECTOR ORESET VOLTAGE REF Tl OUTPUT O T2 OUTPUT 0 1972 3,659,185 3 Sheets-Sheetz F IG 4 INVENTOR JAMES M. GREGOR/CH This invention relates in generalto do to dc converter power transformers and, in particular, to atwo-.core dc to dc converter power transformer capable of operation withsubstantially any practically occurring amount of volt-second unbalanceapplied to the primary coils being compensated for without saturation ofthe cores.

Conventional one-core dc to do converter power transformers are driveninto saturation at one end of their B-I-I'loops when they are operatedwith an unsymmetrical volt-second source. This is particularlynoticeable and objectionable in low-voltage transistor inverters where abalanced drive is virtually impossible to obtain since the semiconductorvoltage drops are a significant portion of the total voltage drop acrossthe transformer.

The reason for such one end saturatiomparticularly with conventionalone-core power transformers, may be understood by considering that when'one of two driving transistors is on the flux level in the core isincreased by an amount equal to g (it Nift and when the other transistoris on the flux in the core is reduced by If these quantities are notequal, with N, and N being two primary transformer coil winding sectionsindividually alternatively driven by the two driving transistors, therewill be a net positive or negative increase in flux subject toaccumulation with each succeeding cycle until the core saturates at plusor minus maximum. Operation then stabilizes around-this point with thecore being driven into saturation to make up the flux unbalance.

It is, therefore, a principal object of this invention to provide atwo-core dc todc converter power transformer capable of operationwithany practically occurring amount of voltsecond unbalance applied to theprimaries without saturating the cores.

Anotherobject with such a two-core dc to do converter power transformeris to achieve desired operation .without saturating the cores withdcsource voltage applied directly across the primary windings.

Features of the invention useful in accomplishing the above objectsinclude, in avolt-second unbalance compensated twocore dc to dcconverter power transformer, two cores alternately on and off with theoff core being reset to saturation by a winding on the on core and acurrent limiter (a resistor in one embodiment) limiting the saturationcurrent. Thus, one core operates from a maximum to somegreater fluxleveland the other core operates from maximum to some lesser flux level.Through proper choice of reset windings and respective reset voltages,the transformer is made to operate with any practically occurring mountof voltsecond unbalance applied to the primaries without saturating thecores and with dc source voltage applied directly across both primarywindings.

A specific embodiment representing what is presently regarded as thebest mode of carrying out the invention is illustrated in theaccompanying drawings.

In the drawings:

FIG. 1 represents a schematic of a conventional prior art one-core dc todc converter power transformer;

FIG. 2, a schematic of applicant's two-core dc to dc converter powertransformer with off core reset windings for both cores;

FIG. 3, another schematic of a two-core dc to dc converter powertransformer with some ofF core reset winding circuit changes from theembodiment of FIG. 2; and

FIG. 4, a family of voltage waveforms at various locations in thetwo-core dc to dc converter power transformer of FIG. 3.

Referring to the drawings:

The prior art one-core dc to dc converter power transformer 10, of FIG.1, has Q and Q NPN transformers 11 and 12 base fed by individual reversesquare wave signal leads 13 and 14 from a suitable signal source 15. Adc power supply 16 has a negative terminal connected in common to theemitters of both NPN transistors 11 and 12, and a relatively positiveterminal connected to a common junction of N and N transformer primarycoils l7 and 18 having other ends connected to the collectors of NPNtransistors 11 and 12, respectively. Transformer primary coils 17 and 18are actually wound on a single transformer core 19, symbolized by ahysteresis curve of a ferrous metal compounded core, having atwo-section secondary coil 20 wound thereon. Tap 21, that may be acenter tap, of secondary coil 20 is connected to one side of load 22 andthe opposite ends of secondary coil 20 are connected individually to theanodes of diodes 23 and 24 the cathodes of which are connected in commonto the other side of load 22.

This prior art dc to do converter transformer 10 is subject to beingdriven into saturation at one end of its B-I-I loop when it is operatedwith an unsymmetrical volt-second source. It is particularly noticeable,and objectionable, in low-voltage transistor inverters where a balanceddrive is virtually impossible to obtain since the semiconductor voltagedrops are a significant part of the total voltage dropped across thetransformer primary coils. With continued reference to FIG. 1 whentransistor O is on, the flux level in the core 19 is in creased by anamount equal to and when O is on the flux in the core is reduced by Ifthese quantities are not equal, there will-be a net positive or negativeincrease in flux, that will accumulate with each succeeding cycle untilthe core saturates at plus or minus 4) maximum. Operation thenstabilizes around this point with the core being driven into saturationto make up the flux unbalance..Consider the following with respect tothe prior art one-core dc todc converter power transformer of FIG. 1.

L (di/dt) N (d/dt) with I sa: p. above Br E dt volt second unbalance icurrent due to volt-second unbalance One end saturation with such aone-core prior art power transformer causes high current spikes at theend of each cycle and acoustic noise if special care is not observed inbuilding the transformer.

Many of the problems and difficulties with the prior art onecore dc todc converter power transformer 10 of FIG. 1 are quite adequatelyresolved with applicant's two-core dc to dc converter power transformerssuch as the two-core embodiment of FIG. 2 with ofFcore reset windingsfor both cores. With thisdc to dc converter power transformer 25, theinput section with O, and O NPN transistors 11 and 12 as fed by signalsource 15 and including dc power supply 16 and the N and N transformerprimary coils 17 and 18 is substantially the same as with the prior artpower transformer of FIG. 1. However, the transformer primary coils 17and 18 are individually wound on the No. 1 and No. 2 cores 26 and 27respectively. The No. 1 and No. 2 magnetic cores 26 and 27 are so spacedthat there is substantially no material magnetic circuit linkagetherebetween and these cores are equipped, respectively, with N and Nsecondary coils 28 and 29 with common polarization as indicated by thedots. Further, the most closely adjacent ends of the secondary coils 28and 29 are connected in common to one side of load 22 just as the tapconnection 21 of coil in the embodiment of FIG. 1 is connected to theload 22 in that embodiment. The other ends of coils 28 and 29 arerespectively connected to the anodes of diodes 23 and 24 with thecathodes connected therefrom in common to the other side of load 22.Still further, the No. 1 core 26 is equipped with an N; and Ntwo-section 30 and 31 coil reset winding 32 and the No. 2 core 27 isequipped with an N and N two-section 33 and 34 coil reset winding 35with the bottom end of coil section 30 connected through currentlimiting resistor 36 to the bottom end of coil 35. Tap 37 between the Nand N coil sections 30 and 31 is connected to the anode of diode 38 witha cathode connection to the upper end of the N coil section 34. Theupper end of the N coil section 31 is connected to the anode of diode 39having a cathode connection to tap 40 between the N and N coil sections33 and 34 of the reset coil 35 for the No.2 core 27.

Through use of two cores 26 and 27 in a dc to do converter transformersuch as the power transformer 25 of FIG 2, the off core may be reset tosaturation by a winding on the on core with the resistor 36 limiting thesaturation current. Thus, one of the cores 26 and 27 operates from aminus (1) maximum to some greater flux level and the other core operatesfrom a positive (1) maximum to some lesser flux level. Throughappropriate choice of reset windings N coil section 33 and N coilsection 30 and the reset voltages E; and E across the respective resetcoil sections, the transformer can be made to operate with anypractically occurring amount of voltsecond unbalance applied to theprimary coil windings l7 and 18 without saturating the cores 26 and 27with the dcsupply 16 source voltage applied directly across the primarycoil windings l7 and 18. With the embodiment of FIG. 2 assuming that theturns N or primary coil 17 equal N the number of turns of primary coil18 and that with the reset coils 32 and 35 that N; equals N equals Nequals N and further that N, equals 2 N Further, with No. 1 core 26substantially equal to the No. 2 core 27, and operation started with,for example, Q, coming on and both cores previously at zero flux, sinceE, is a square wave voltage ofT seconds, the flux added to the No. 1core 26 is:

reset If enough volt-seconds are added to the N core 17 to equal a fluxlevel of six units, then the number 2 core 27 would saturate when theflux level of the N core 17 reached four units. The resistor 36 isprovided and of such value as to prevent excessive current when eitherof the cores 26 and 27 saturates. When the Q NPN transistor 12 turns onvoltages of the circled polaries are developed and the flux in the No. 2core 27 is given by Let Q5 unbalance two units, and then while O is on"the No. 1 core 26 is reset by the N winding 30 and the reset flux is:

If the No. 2 core 27 receives a flux change of eight units, the

flux in the No. 1 core 26 is reset by minus 12 units. Since the No. 1core was already at plus six units, his now saturated at minus maximum.When the Q NPN transistor 11 comes on, the flux level of the No. 1 core26 will be increased again by six units from minus 4) maximum to 0 andthe reset voltage on the N winding 33 section of reset coil 35 willdrive the No. 2 core 27 to a positive d) maximum. When the Q NPNtransistor 12 comes on again, the flux density in the No. 2 core 27 willbe decreased by eight units from a positive maximum to minus 2 and theNo. 1 core 26 will be driven back to maximum. Thus, each core willoperate from one end of its B-I-I loop to somewhere in the center. Withthe particular reset windings and voltages selected, the transformer canbe made to operate with a maximum volt second unbalance of 3/2 4)minimum 4: minimum or one-half the minimum flux excursion. By choosingother reset voltages, and number of turns, the transformer can be madeto operate with more or less unbalance as the case may be.

The two-core dc to dc converter power transformer embodiment of FIG. 3includes portions duplicating portions of the FIG. 2 embodiment numberedthe same and description of portions that are the same are notnecessarily repeated again. In this embodiment primary coils l7 and 18are indicated as being 19-turn coils and the secondarY output coils 28'and 29 are indicated as being 28-turn coils. The phase polarity ofsecondary coils 28' and 29' are indicated by the dots as being oppositethat with coils 28 and 29 in the embodiment of FIG. 2; however, within asingle working unit as long as the phase polarity is consistent, theoperational results should be effectively the same. In FIG. 3, the resetcoils 32' and 35 and the interconnecting circuitry is somewhat differentthan with reset coils 32 and 35 and the interconnecting circuitry inFIG. 2

with reset coil 32' having a lower l6-turn section 41 and an upper27-turn section 42 with the sections separated by tap 43. Reset coil 35has, in like manner, a lower l6-turn coil section 44 and an upper27-turn coil section 45 with the sections separated by tap 46. The upperend of reset coil 32 and of the coil section 42 is connected to acurrent limiter 36' and through the current limiter to the top of resetcoil 35 and the coil section 45. In this instance, the current limiter36' is in the form of a current limiting diode with the anode connectedto coil section 42 and the cathode connected to coil section 45. The tap46 of reset coil 35 is connected to the anode of diode 38' having acathode connection to the bottom of section 41 of reset coil 32 and thebottom of section 44 of reset coil 35 is connected to the anode of diode39 having a cathode connection to the tap 43 of reset coil 32'.

Referring also to FIG. 4, Q base drive and Q base drive to N PNtransistors 12 and 11 from the signal source 15 are shown as beingopposite phase square waves varying from plus 1 volt to minus 1 volt andthe Q and Q collector voltage waveforms are voltages appearing in thecollector to transformer primary coil connective lines. The resetvoltage waveform shows a waveform ranging from just below 0 volts to aslow as minus 40 volts with spikes even going to a lower negative voltagemeasured across reset coil 32 whereas the corresponding waveformmeasured across reset coil 35' would be a duplicate inverted waveform ofthe reset voltage waveform shown going to positive voltages instead ofthe negative voltages that are shown. The resulting T, and T outputwaveforms ranging between a positive 28 volts and a negative 45 voltsare the outputs developed from power transformer secondary coils 29 and28 and delivered to load 22 as rectified by diodes 23 and 24. It is ofinterest to note that the voltage appearing on the collector to primarycoil interconnects to coils 17 and 18 drop respectively fromapproximately positive 50 volts to the 20 volts supplied by dc supply 16during each reset cycle for the respective core 26 or 27 as reset tominimum or maximum (1) is attained as the case may be. These 20 voltwaveform porches on the transistor collector to primary coil connectivelines are coincident with the 40 volt level portions of the resetvoltage, as varied by spikes due to nonideal transformer parameters, andalso coincident with zero voltage level portions of one or the other ofthe T and T output waveforms.

Whereas this invention is herein illustrated and described with respectto two embodiments hereof, it should be realized that various changesmay be made without departing from essential contributions to the artmade by the teachings hereof.

lclaim:

1. In a dc to dc converter power transformer; two magnetic materialcores; a first primary coil on one, and a second primary coil on theother of said two magnetic material cores; dc power supply means; switchmeans for alternatively applying dc to said first and second primarycoils connected to said dc power supply means and to said first andsecond primary coils; a first secondary coil on one, and a secondsecondary coil on the other of said two magnetic material cores; signalrectifying output to load connective circuit means connected to saidfirst and second secondary coils; a first reset coil on one, and asecond reset coil on the other of said two magnetic material cores; andcircuit interconnect means between said first reset coil and said secondreset coil including rectifying means.

2. The dc to dc converter power transformer of claim 1, wherein saidrectifying means is diode means.

3. The dc to dc converter of claim 2, wherein said first and secondreset coils each include first and second opposite ends and a coil tap;with said circuit interconnect means including, a circuitinterconnection between said first ends of said first and second resetcoils, a connection through a first diode from the tap of said firstreset coil to the second opposite end of said second reset coil, and aconnection through a second diode from the second opposite end of saidfirst reset coil to the tap of said second reset coil; and with commonelectrodes of said first and second diodes connected to said first resetcoil.

4. The dc to dc converter of claim 3, wherein current llmlling means isincluded in said circuit interconnection between said first ends of thereset coils.

5. The dc to dc converter of claim 4, wherein said current limitingmeans is a resistor.

6. The dc to dc converter of claim 4, wherein said current limitingmeans is a current limiting field effect diode.

7. The dc to dc converter of claim 4, wherein said taps of said firstand second reset coils are center taps.

8. The dc to dc converter of claim 4, wherein said taps are off centertaps in said first and second reset coils.

1. In a dc to dc converter power transformer; two magnetic materialcores; a first primary coil on one, and a second primary coil on theother of said two magnetic material cores; dc power supply means; switchmeans for alternatively applying dc to said first and second primarycoils connected to said dc power supply means and to said first andsecond primary coils; a first secondary coil on one, and a secondsecondary coil on the other of said two magnetic material cores; signalrectifying output to load connective circuit means connected to saidfirst and second secondary coils; a first reset coil on one, and asecond reset coil on the other of said two magnetic material cores; andcircuit interconnect means between said first reset coil and said secondreset coil including rectifying means.
 2. The dc to dc converter powertransformer of claim 1, wherein said rectifying means is diode means. 3.The dc to dc converter of claim 2, wherein said first and second resetcoils each include first and second opposite ends and a coil tap; withsaid circuit interconnect means including, a circuit interconnectionbetween said first ends of said first and second reset coils, aconnection through a first diode from the tap of said first reset coilto the second opposite end of said second reset coil, and a connectionthrough a second diode from the second opposite end of said first resetcoil to the tap of said second reset coil; and with common electrodes ofsaid first and second diodes connected to said first reset coil.
 4. Thedc to dc converter of claim 3, wherein current limiting means isincluded in said circuit interconnection between said first ends of thereset coils.
 5. The dc to dc converter of claim 4, wherein said currentlimiting means is a resistor.
 6. The dc to dc converter of claim 4,wherein said current limiting means is a current limiting field effectdiode.
 7. The dc to dc converter of claim 4, wherein said taps of saidfirst and second reset coils are center taps.
 8. The dc to dc converterof claim 4, wherein said taps are off center taps in said first andsecond reset coils.